As the density of integrated circuits continues to increase, the scaling down of the semiconductor device feature sizes in integrated circuits (“ICs”) has followed. This trend poses continuous technical challenges in manufacturing ICs with improved performance. For example, it has been widely recognized that, when device feature sizes shrink down to the ultra-deep submicron range (less than 0.25 micron), interconnect (also generally referred to as “net”) delays between devices in an IC, due to parasitic resistance/capacitance on the nets, begin to dominate the overall time delay in an IC. As a consequence, significant efforts have been taken by IC design engineers in extracting parasitic net capacitance by improved accuracy so that IC designers can predict the impact of the parasitic effects in an early design stage and compensate for these detrimental effects through proper design optimization steps.
Currently, extraction efforts are mainly focused on the coupling capacitance between adjacent nets. Accurate models have been developed for predicting time delays due to net-to-net parasitic capacitance. However, the parasitic capacitance associated with the contacts and vias, which are formed in an IC to couple a net with a device node and to connect nets in different interconnect layers, is either ignored or estimated with poor accuracy. When the trend of device scaling in an IC continues, the existing extraction methodology is problematic for various reasons. Firstly, contact and via capacitance accounts for a significantly increased proportion of the total interconnect delay in ICs made with advanced technology, due to the reduced contact-to-gate-electrode spacing and increased contact and via density. Interconnect parasitic extraction ignoring parasitic effects on contacts and vias may lead to significant discrepancy between circuit simulation results and the actual circuit performance.
Secondly, in existing parasitic extraction system, a per-unit contact and via capacitance value derived from an ideal, square-shaped contact and via primitive is typically used to calculate the contact and via parasitic capacitance in an IC. The aforementioned per-unit contact and via capacitance value is typically calculated by a field solver, and the actual contact/via shapes and size variations due to IC manufacturing process variation are generally ignored. This may, in turn, lead to inaccurate parasitic extraction on contacts and vias in an actual IC. In existing practices, the contact-to-gate-electrode capacitance in an IC is generally overestimated, while the via-to-via capacitance in an IC is typically underestimated by a margin of as large as about 10% in certain circumstances.
In view of the foregoing, it has become very important to perform parasitic extraction in an IC with the actual contact/via shapes and size variations in consideration. This is accomplished through the invention fully described in the commonly assigned patent application Ser. No. 11/865,304 filed on Oct. 1, 2007, entitled “Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits” (TSM07-0376), which application is hereby incorporated herein by reference. In the aforementioned reference, contact and via capacitance models are developed for contacts and vias occurring in an actual IC. Each contact and via model possesses an ideal contact and via configuration (e.g., square shape without taped cross-sectional dimension) recognizable by the existing extraction tools, while having a matching capacitance with that of an actual contact and via. The capacitance matching is performed through mapping an actual contact/via configuration occurring in an IC into an ideal, square-shaped, extracting-tool-recognizable contact/via configuration having an “effective (contact/via) width.” Using capacitance models thus created, parasitic extraction on an IC in an existing extracting system and the circuit simulation based there upon will match with the actual performance of an IC. Nevertheless, creating the desired contact and via models requires first and foremost making accurate measurement of parasitic capacitance on contact and via that have the shapes and size variations occurring in an actual IC.
FIG. 1 illustrates a schematic cross-section view of a known test structure used in measuring contact-to-gate-electrode capacitance Cco—po on an MOSFET transistor occurring in an IC. FIG. 1 shows one unit of interest on a contact-to-gate-electrode capacitance test structure for clearer view. In practice, a large number of units typically present in a test structure in order to bring the capacitance of interest to a measurable scale, since capacitance on a single unit is negligibly small when compared to other capacitance components in an IC. Contacts “c” are formed coupling a metal wire M1 in the first interconnect layer with the source/drain regions “s” and “d,” respectively. A known capacitance meter coupling to the gate electrode “g” and one of the M1 wires is used to measure the contact-to-gate-electrode capacitance, labeled as Cco—po in FIG. 1. However, this prior art test structure and method of measuring Cco—po suffer from significant deficiencies because, besides the to-be-measured contact-to-gate-electrode capacitance Cco—po, the gate-to-metal capacitance Cg-ml, the junction capacitance Cgs, and the metal-to-metal capacitance Cml—ml are inevitably introduced into the measurements.